Verilog code coverage analysis tool
Covered is a Verilog code coverage utility that reads in a Verilog design and
a generated VCD/LXT dumpfile from that design and generates a coverage file
that can be merged with other coverage files or used to create a coverage
report. Covered also contains the GUI coverage report utility that reads in a
coverage file to allow interactive coverage discovery. Areas of coverage
measured by Covered are: line, toggle, memory, combinational logic, FSM
state/state-transition and assertion coverage.
For information regarding...
* the installation of Covered, see the INSTALL file.
* a list of the developers of Covered, see the AUTHORS file.
* the CVS change list, see the ChangeLog file.
* project-specific news, see the NEWS file.
For User documentation...
* User's Guide can be found in HTML form at ./doc/html/index.html.
* Command-line help can be found by typing "covered -h" after Covered
Stable release covered-0.7.10 made. This release updates the FST library to the latest version which contains some fixes and
Covered(1) Code Analysis Covered(1)
Covered - Verilog Code Coverage Analyzer
covered [global_options] score [options]
covered [global_options] merge [options] existing_database
covered [global_options] report [options] database_file
covered [global_options] rank [options] database_
covered (0.7.10-1) unstable; urgency=low
* New upstream release.
* Refreshed manpage.diff patch
2010-12-02 00:48 phase1geo
Updating files to 0.7.10 version for next stable release.
The following items are known to be problems in the current code that need to be fixed
or features t
Browse inside covered_0.7.10-1_sparc.deb
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