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LVS netlist comparison tool for VLSI

Netgen is a tool for comparing netlists, a process known as LVS, which stands for "Layout vs. Schematic". This is an important step in the integrated circuit design flow, ensuring that the geometry that has been laid out matches the expected circuit.

The greatest need for LVS is in large analog or mixed-signal circuits that cannot be simulated in reasonable time. Even for small circuits, LVS can be done much faster than simulation, and provides feedback that makes it easier to find an error than does a simulation.

Package version:1.3.7

Browse inside netgen-1.3.7-21.fc17.src.rpm

1.09 KB2014-11-27HEADER  view  126 mirrors
603 B2014-11-27netgen-1.3.7-free.patch  view  4 mirrors
334.15 KB2014-11-27netgen-1.3.7.tgz  4 mirrors
187 B2014-11-27netgen.desktop  view  4 mirrors
542 B2014-11-27netgen.png  9 mirrors
5.55 KB2014-11-27netgen.spec  view  4 mirrors

Download netgen-1.3.7-21.fc17.src.rpm

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