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Netlist(3pm)     User Contributed Perl Documentation    Netlist(3pm)

       Verilog::Netlist - Verilog Netlist

           use Verilog::Netlist;

           # Setup options so files can be found
           use Verilog::Getopt;
           my $opt = new Verilog::Getopt;
           $opt->parameter( "+incdir+verilog",

           # Prepare netlist
           my $nl = new Verilog::Netlist (options => $opt,);
           foreach my $file ('testnetlist.v') {
               $nl->read_file (filename=>$file);
           # Read in any sub-modules
           #$nl->lint();  # Optional, see docs; probably not wanted

           foreach my $mod ($nl->top_modules_sorted) {
               show_hier ($mod, "  ", "", "");

           sub show_hier {
               my $mod = shift;
               my $indent = shift;
               my $hier = shift;
               my $cellname = shift;
               if (!$cellname) {$hier = $mod->name;} #top modules get the design name
               else {$hier .= ".$cellname";} #append the cellname
               printf ("%-45s %s\n", $indent."Module ".$mod->name,$hier);
               foreach my $sig ($mod->ports_sorted) {
                   printf ($indent."     %sput %s\n", $sig->direction, $sig->name);
               foreach my $cell ($mod->cells_sorted) {
                   printf ($indent. "    Cell %s\n", $cell->name);
                   foreach my $pin ($cell->pins_sorted) {
                       printf ($indent."     .%s(%s)\n", $pin->name, $pin->netname);
                   show_hier ($cell->submod, $indent."  ", $hier, $cell->name) if $cell->submod;

       Verilog::Netlist reads and holds interconnect information
       about a whole design database.

       See the "Which Package" section of Verilog::Language if you
       are unsure which parsing package to use for a new

       A Verilog::Netlist is composed of files, which contain the
       text read from each file.

       A file may contain modules, which are individual blocks that
       can be instantiated (designs, in Synopsys terminology.)

       Modules have ports, which are the interconnection between
       nets in that module and the outside world.  Modules also have
       nets, (aka signals), which interconnect the logic inside that

       Modules can also instantiate other modules.  The
       instantiation of a module is a Cell.  Cells have pins that
       interconnect the referenced module's pin to a net in the
       module doing the instantiation.

       Each of these types, files, modules, ports, nets, cells and
       pins have a class.  For example Verilog::Netlist::Cell has
       the list of Verilog::Netlist::Pin (s) that interconnect that

       See also Verilog::Netlist::Subclass for additional accessors
       and methods.

           Error checks the entire netlist structure.  Currently
           there are only two checks, that modules are bound to
           instantiations (which is also checked by $netlist->link),
           and that signals aren't multiply driven.  Note that as
           there is no elaboration you may get false errors about
           multiple drivers from generate statements that are
           mutually exclusive.  For this reason and the few lint
           checks you may not want to use this method.
           Alternatively to avoid pin interconnect checks, set the
           $netlist->new (...use_vars=>0...) option.

           Resolves references between the different modules.

           If link_read=>1 is passed when netlist->new is called (it
           is by default), undefined modules will be searched for
           using the Verilog::Getopt package, passed by a reference
           in the creation of the netlist.  To suppress errors in
           any missing references, set link_read_nonfatal=>1 also.

           Creates a new netlist structure.  Pass optional
           parameters by name, with the following parameters:

           implicit_wires_ok => $true_or_false
                   Indicates whether to allow undeclared wires to be

           include_open_nonfatal => $true_or_false
                   Indicates that include files that do not exist
                   should be ignored.

           keep_comments => $true_or_false
                   Indicates that comment fields should be preserved
                   and on net declarations into the
                   Vtest::Netlist::Net structures.  Otherwise all
                   comments are stripped for speed.

           link_read => $true_or_false
                   Indicates whether or not the parser should
                   automatically search for undefined modules
                   through the "options" object.

           link_read_nonfatal => $true_or_false
                   Indicates that modules that referenced but not
                   found should be ignored, rather than causing an
                   error message.

           lint_pin_interconnect => $true_or_false
                   Indicates that lint should Interconnect
                   information is not needed, do not read it, nor
                   report lint related pin warnings.  Greatly
                   improves performance.

           logger => object
                   Specify a message handler object to be used for
                   error handling, this class should be a
                   Verilog::Netlist::Logger object, or derived from
                   one.  If unspecified, a Verilog::Netlist::Logger
                   local to this netlist will be used.

           options => $opt_object
                   An optional pointer to a Verilog::Getopt object,
                   to be used for locating files.

           preproc => $package_name
                   The name of the preprocessor class. Defaults to

           use_vars => $true_or_false
                   Indicates that signals, variables, and pin
                   interconnect information is needed; set by
                   default.  If clear do not read it, nor report
                   lint related pin warnings, which can greatly
                   improve performance.

           Prints debugging information for the entire netlist

           Returns Verilog::Netlist::Interface matching given name.

           Returns list of Verilog::Netlist::Interface.

           Returns name sorted list of Verilog::Netlist::Interface.

           Creates a new Verilog::Netlist::Interface.

           Returns Verilog::Netlist::Module matching given name.

           Returns list of Verilog::Netlist::Module.

           Returns name sorted list of Verilog::Netlist::Module.

           Returns level sorted list of Verilog::Netlist::Module.
           Leaf modules will be first, the top most module will be

           Creates a new Verilog::Netlist::Module.

           Returns name sorted list of Verilog::Netlist::Module,
           only for those modules which have no children and are not
           unused library cells.

           Writes a dependency file for make, listing all input and
           output files.

       $netlist->defvalue_nowarn (define)
           Return the value of the specified define or undef.

           Adds an additional input dependency for dependency_write.

           Adds an additional output dependency for

           Delete the netlist, reclaim memory.  Unfortunately
           netlists will not disappear simply with normal garbage
           collection from leaving of scope due to complications
           with reference counting and weaking Class::Struct
           structures; solutions welcome.

           Returns list of Verilog::Netlist::File.

           Returns a name sorted list of Verilog::Netlist::File.

           Returns Verilog::Netlist::File matching given name.

       $netlist->read_file( filename=>$name)
           Reads the given Verilog file, and returns a
           Verilog::Netlist::File reference.

           Generally called as $netlist->read_file.  Pass a hash of
           parameters.  Reads the filename=> parameter, parsing all
           instantiations, ports, and signals, and creating
           Verilog::Netlist::Module structures.

       $netlist->read_libraries ()
           Read any libraries specified in the options=> argument
           passed with the netlist constructor.  Automatically
           invoked when netlist linking results in a module that
           wasn't found, and thus might be inside the libraries.

       $netlist->remove_defines (string)
           Expand any `defines in the string and return the results.
           Undefined defines will remain in the returned string.

       $netlist->resolve_filename (string, [lookup_type])
           Convert a module name to a filename.  Optional
           lookup_type is 'module', 'include', or 'all', to use only
           module_dirs, incdirs, or both for the lookup.  Return
           undef if not found.

           Returns verilog code which represents the netlist.

       Cell instantiations without any arguments are not supported,
       a empty set of parenthesis are required.  (Use "cell
       cell();", not "cell cell;".)

       Order based pin interconnect is not supported, use name based

       Verilog-Perl is part of the <> free
       Verilog EDA software tool suite.  The latest version is
       available from CPAN and from

       Copyright 2000-2010 by Wilson Snyder.  This package is free
       software; you can redistribute it and/or modify it under the
       terms of either the GNU Lesser General Public License Version
       3 or the Perl Artistic License Version 2.0.

       Wilson Snyder <>

       Verilog-Perl, Verilog::Netlist::Cell, Verilog::Netlist::File,
       Verilog::Netlist::Interface, Verilog::Netlist::Logger,
       Verilog::Netlist::ModPort, Verilog::Netlist::Module,
       Verilog::Netlist::Net, Verilog::Netlist::Pin,
       Verilog::Netlist::Port, Verilog::Netlist::Subclass

       And the <>Verilog-Mode
       package for Emacs.

perl v5.10.1                 2010-06-29                 Netlist(3pm)
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